? semiconductor components industries, llc, 2001 february, 2001 rev. 3 1 publication order number: mtp3055v/d mtp3055v preferred device power mosfet 12 amps, 60 volts nchannel to220 this power mosfet is designed to withstand high energy in the avalanche and commutation modes. designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? onresistance area product about onehalf that of standard mosfets with new low voltage, low r ds(on) technology ? faster switching than efet predecessors ? avalanche energy specified ? i dss and v ds(on) specified at elevated temperature ? static parameters are the same for both tmos v and tmos efet maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drainsource voltage v dss 60 vdc draingate voltage (r gs = 1.0 m w ) v dgr 60 vdc gatesource voltage continuous nonrepetitive (t p 10 ms) v gs v gsm 20 25 vdc vpk drain current continuous @ 25 c drain current continuous @ 100 c drain current single pulse (t p 10 m s) i d i d i dm 12 7.3 37 adc apk total power dissipation @ 25 c derate above 25 c p d 48 0.32 watts w/ c operating and storage temperature range t j , t stg 55 to 175 c single pulse draintosource avalanche energy starting t j = 25 c (v dd = 25 vdc, v gs = 10 vdc, i l = 12 apk, l = 1.0 mh, r g = 25 w ) e as 72 mj thermal resistance junction to case thermal resistance junction to ambient r q jc r q ja 3.13 62.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 12 amperes 50 volts r ds(on) = 150 m w preferred devices are recommended choices for future use and best overall value. device package shipping ordering information mtp3055v to220ab 50 units/rail to220ab case 221a style 5 1 2 3 4 http://onsemi.com nchannel d s g marking diagram & pin assignment mtp3055v = device code ll = location code y = year ww = work week mtp3055v llyww 1 gate 3 source 4 drain 2 drain
mtp3055v http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drainsource breakdown voltage (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 60 65 vdc mv/ c zero gate voltage drain current (v ds = 60 vdc, v gs = 0 vdc) (v ds = 60 vdc, v gs = 0 vdc, t j = 150 c) i dss 10 100 m adc gatebody leakage current (v gs = 20 vdc, v ds = 0) i gss 100 nadc on characteristics (note 1.) gate threshold voltage (v ds = v gs , i d = 250 m adc) temperature coefficient (negative) v gs(th) 2.0 2.7 5.4 4.0 vdc mv/ c static drainsource onresistance (v gs = 10 vdc, i d = 6.0 adc) r ds(on) 0.10 0.15 ohm drainsource onvoltage (v gs = 10 vdc) (i d = 12 adc) (i d = 6.0 adc, t j = 150 c) v ds(on) 1.3 2.2 1.9 vdc forward transconductance (v ds = 7.0 vdc, i d = 6.0 adc) g fs 4.0 5.0 mhos dynamic characteristics input capacitance (v 25 vd v 0 vd c iss 410 500 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss 130 180 reverse transfer capacitance f = 1 . 0 mhz) c rss 25 50 switching characteristics (note 2.) turnon delay time t d(on) 7.0 10 ns rise time (v dd = 30 vdc, i d = 12 adc, v gs =10vdc t r 34 60 turnoff delay time v gs = 10 vdc, r g = 9.1 w ) t d(off) 17 30 fall time r g 9.1 w ) t f 18 50 gate charge (s fi 8) q t 12.2 17 nc (see figure 8) (v ds = 48 vdc, i d = 12 adc, q 1 3.2 (v ds 48 vdc , i d 12 adc , v gs = 10 vdc) q 2 5.2 q 3 5.5 sourcedrain diode characteristics forward onvoltage (note 1.) (i s = 12 adc, v gs = 0 vdc) (i s = 12 adc, v gs = 0 vdc, t j = 150 c) v sd 1.0 0.91 1.6 vdc reverse recovery time (s fi 15) t rr 56 ns (see figure 15) (i s =12adc v gs = 0 vdc t a 40 (i s = 12 adc, v gs = 0 vdc, di s /dt = 100 a/ m s) t b 16 reverse recovery stored charge di s /dt = 100 a/ m s) q rr 0.128 m c internal package inductance internal drain inductance (measured from contact screw on tab to center of die) (measured from the drain lead 0.25 from package to center of die) l d 3.5 4.5 nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s 7.5 nh 1. pulse test: pulse width 300 m s, duty cycle 2%. 2. switching characteristics are independent of operating junction temperature.
mtp3055v http://onsemi.com 3 typical electrical characteristics r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (normalized) 01234 5 0 8 16 24 v ds , drain-to-source voltage (volts) figure 1. onregion characteristics i d , drain current (amps) 24 6 810 0 8 16 24 i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 2. transfer characteristics 048 16 24 0 0.10 0.20 0.30 r ds(on) , drain-to-source resistance (ohms) 0 8 20 24 0.08 0.09 0.13 0.15 i d , drain current (amps) figure 3. onresistance versus drain current and temperature i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage -50 0.6 0.8 1.2 1.6 020 5060 1 10 100 t j , junction temperature ( c) figure 5. onresistance variation with temperature v ds , drain-to-source voltage (volts) figure 6. draintosource leakage current versus voltage i dss , leakage (na) -25 0 25 50 75 100 125 150 t j = 25 c v ds 10 v t j = -55 c 25 c 100 c t j = 25 c v gs = 0 v v gs = 10 v v gs = 10 v i d = 6 a 9 v 8 v 6 v 5 v 4 v 7 v 4 12 20 3579 4 12 20 v gs = 10 v t j = 100 c 25 c -55 c 12 20 4 12 16 10 30 40 0.05 0.15 0.25 0.10 0.12 0.14 0.11 1.0 1.4 t j = 125 c v gs = 10 v 15 v 175
mtp3055v http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. 10 0 10 15 25 gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) figure 7. capacitance variation v gs v ds t j = 25 c v ds = 0 v v gs = 0 v 1200 1000 800 600 400 200 0 20 c iss c oss c rss 55 c iss c rss
mtp3055v http://onsemi.com 5 v ds , drain-to-source voltage (volts) v gs , gate-to-source voltage (volts) draintosource diode characteristics 0.50 0.60 0.70 0.80 1.0 v sd , source-to-drain voltage (volts) figure 8. gatetosource and draintosource voltage versus total charge i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 t, time (ns) v dd = 30 v i d = 12 a v gs = 10 v t j = 25 c t f t d(off) v gs = 0 v t j = 25 c figure 10. stored charge 0 q t , total charge (nc) 2468 13 i d = 12 a t j = 25 c v gs 0 6 8 10 12 1000 100 10 1 10 6 2 0 12 8 4 60 50 40 30 20 10 0 v ds 13579 4 0.55 0.65 0.75 0.85 0.90 2 0.95 qt q1 q2 q3 11 10 12 t d(on) t r 04 12 i s , source current (amps) q rr , stored charge ( c) dis/dt = 100 a/ m s v dd = 25 v t j = 25 c 0.08 0.10 0.11 0.12 0.13 0.09 26810 figure 11. diode forward voltage versus current m safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistancegeneral data and its use.o switching between the offstate and the onstate may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. although many efets can withstand the stress of draintosource avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 13). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
mtp3055v http://onsemi.com 6 safe operating area t j , starting junction temperature ( c) e as , single pulse drain-to-source figure 12. maximum rated forward biased safe operating area 0.1 10 100 v ds , drain-to-source voltage (volts) figure 13. maximum avalanche energy versus starting junction temperature avalanche energy (mj) i d , drain current (amps) 25 50 75 100 125 v gs = 20 v single pulse t c = 25 c i d = 12 a 1.0 150 t, time (s) figure 14. thermal response r(t), normalized effective transient thermal resistance r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 figure 15. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 1.0 100 0.1 0 75 25 10 1.0 0.1 0.01 0.2 d = 0.5 0.05 0.01 single pulse 0.1 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 dc 100 m s 1 ms 10 ms 10 m s r ds(on) limit thermal limit package limit 50 0.02 175
mtp3055v http://onsemi.com 7 package dimensions to220 threelead to220ab case 221a09 issue aa style 5: pin 1. gate 2. drain 3. source 4. drain notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 --- 1.15 --- z --- 0.080 --- 2.04 b q h z l v g n a k f 123 4 d seating plane t c s t u r j
mtp3055v http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mtp3055v/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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